Rabu, 17 Desember 2008



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Simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per cycle can be completed.
Processor board of a CRAY T3e supercomputer with four superscalar Alpha 21164 processors

A superscalar CPU architecture implements a form of parallelism called instruction-level parallelism within a single processor. It thereby allows faster CPU throughput than would otherwise be possible at the same clock rate. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.

While a superscalar CPU is typically also pipelined, they are two different performance enhancement techniques. It is theoretically possible to have a non-pipelined superscalar CPU or a pipelined non-superscalar CPU.

The superscalar technique is traditionally associated with several identifying characteristics. Note these are applied within a given CPU core.

  • Instructions are issued from a sequential instruction stream
  • CPU hardware dynamically checks for data dependencies between instructions at run time (versus software checking at compile time)
  • Accepts multiple instructions per clock cycle




Seymour Cray's CDC 6600 from 1965 is often mentioned as the first superscalar design. The Intel i960CA (1988) and the AMD 29000-series 29050 (1990) microprocessors were the first commercial single chip superscalar microprocessors. RISC CPUs like these brought the superscalar concept to micro computers because the RISC design results in a simple core, allowing straightforward instruction dispatch and the inclusion of multiple functional units (such as ALUs) on a single CPU in the constrained design rules of the time. This was the reason that RISC designs were faster than CISC designs through the 1980s and into the 1990s.

Except for CPUs used in some battery-powered devices, essentially all general-purpose CPUs developed since about 1998 are superscalar. Beginning with the "P6" (Pentium Pro and Pentium II) implementation, Intel's x86 architecture microprocessors have implemented a CISC instruction set on a superscalar RISC microarchitecture. Complex instructions are internally translated to a RISC-like "micro-ops" RISC instruction set, allowing the processor to take advantage of the higher-performance underlying processor while remaining compatible with earlier Intel processors.

From scalar to superscalar

The simplest processors are scalar processors. Each instruction executed by a scalar processor typically manipulates one or two data items at a time. By contrast, each instruction executed by a vector processor operates simultaneously on many data items. An analogy is the difference between scalar and vector arithmetic. A superscalar processor is sort of a mixture of the two. Each instruction processes one data item, but there are multiple redundant functional units within each CPU thus multiple instructions can be processing separate data items concurrently.

Superscalar CPU design emphasizes improving the instruction dispatcher accuracy, and allowing it to keep the multiple functional units in use at all times. This has become increasingly important when the number of units increased. While early superscalar CPUs would have two ALUs and a single FPU, a modern design such as the PowerPC 970 includes four ALUs, two FPUs, and two SIMD units. If the dispatcher is ineffective at keeping all of these units fed with instructions, the performance of the system will suffer.

A superscalar processor usually sustains an execution rate in excess of one instruction per machine cycle. But merely processing multiple instructions concurrently does not make an architecture superscalar, since pipelined, multiprocessor or multi-core architectures also achieve that, but with different methods.

In a superscalar CPU the dispatcher reads instructions from memory and decides which ones can be run in parallel, dispatching them to redundant functional units contained inside a single CPU. Therefore a superscalar processor can be envisioned having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread.


Available performance improvement from superscalar techniques is limited by two key areas:

  1. The degree of intrinsic parallelism in the instruction stream, i.e. limited amount of instruction-level parallelism, and
  2. The complexity and time cost of the dispatcher and associated dependency checking logic.

Existing binary executable programs have varying degrees of intrinsic parallelism. In some cases instructions are not dependent on each other and can be executed simultaneously. In other cases they are inter-dependent: one instruction impacts either resources or results of the other. The instructions a = b + c; d = e + f can be run in parallel because none of the results depend on other calculations. However, the instructions a = b + c; d = a + f might not be runnable in parallel, depending on the order in which the instructions complete while they move through the units.

When the number of simultaneously issued instructions increases, the cost of dependency checking increases extremely rapidly. This is exacerbated by the need to check dependencies at run time and at the CPU's clock rate. This cost includes additional logic gates required to implement the checks, and time delays through those gates. Research shows the gate cost in some cases may be nk gates, and the delay cost k2logn, where n is the number of instructions in the processor's instruction set, and k is the number of simultaneously dispatched instructions. In mathematics, this is called a combinatoric problem involving permutations.

Even though the instruction stream may contain no inter-instruction dependencies, a superscalar CPU must nonetheless check for that possibility, since there is no assurance otherwise and failure to detect a dependency would produce incorrect results.

No matter how advanced the semiconductor process or how fast the switching speed, this places a practical limit on how many instructions can be simultaneously dispatched. While process advances will allow ever greater numbers of functional units (e.g, ALUs), the burden of checking instruction dependencies grows so rapidly that the achievable superscalar dispatch limit is fairly small. -- likely on the order of five to six simultaneously dispatched instructions.

However even given infinitely fast dependency checking logic on an otherwise conventional superscalar CPU, if the instruction stream itself has many dependencies, this would also limit the possible speedup. Thus the degree of intrinsic parallelism in the code stream forms a second limitation.



Pipelining redirects here. For HTTP pipelining, see HTTP pipelining.
Basic five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). The vertical axis is successive instructions, the horizontal axis is time. So in the green column, the earliest instruction is in WB stage, and the latest instruction is undergoing instruction fetch.

An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time).

The fundamental idea is to split the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once. The term pipeline refers to the fact that each step is carrying data at once (like water), and each step is connected to the next (like the links of a pipe.)

The origin of pipelining is thought to be either the ILLIAC II project or the IBM Stretch project. The IBM Stretch Project proposed the terms, "Fetch, Decode, and Execute" that became common usage.

Most modern CPUs are driven by a clock. The CPU consists internally of logic and memory (flip flops). When the clock signal arrives, the flip flops take their new value and the logic then requires a period of time to decode the new values. Then the next clock pulse arrives and the flip flops again take their new values, and so on. By breaking the logic into smaller pieces and inserting flip flops between the pieces of logic, the delay before the logic gives valid outputs is reduced. In this way the clock period can be reduced. For example, the RISC pipeline is broken into five stages with a set of flip flops between each stage.

  1. Instruction fetch
  2. Instruction decode and register fetch
  3. Execute
  4. Memory access
  5. Register write back

Hazards: When a programmer (or compiler) writes assembly code, they make the assumption that each instruction is executed before execution of the subsequent instruction is begun. This assumption is invalidated by pipelining. When this causes a program to behave incorrectly, the situation is known as a hazard. Various techniques for resolving hazards such as forwarding and stalling exist.

A non-pipeline architecture is inefficient because some CPU components (modules) are idle while another module is active during the instruction cycle. Pipelining does not completely cancel out idle time in a CPU but making those modules work in parallel improves program execution significantly.

Processors with pipelining are organized inside into stages which can semi-independently work on separate jobs. Each stage is organized and linked into a 'chain' so each stage's output is fed to another stage until the job is done. This organization of the processor allows overall processing time to be significantly reduced.

Unfortunately, not all instructions are independent. In a simple pipeline, completing an instruction may require 5 stages. To operate at full performance, this pipeline will need to run 4 subsequent independent instructions while the first is completing. If 4 instructions that do not depend on the output of the first instruction are not available, the pipeline control logic must insert a stall or wasted clock cycle into the pipeline until the dependency is resolved. Fortunately, techniques such as forwarding can significantly reduce the cases where stalling is required. While pipelining can in theory increase performance over an unpipelined core by a factor of the number of stages (assuming the clock frequency also scales with the number of stages), in reality, most code does not allow for ideal execution.



Advantages and Disadvantages

Pipelining does not help in all cases. There are several possible disadvantages. An instruction pipeline is said to be fully pipelined if it can accept a new instruction every clock cycle. A pipeline that is not fully pipelined has wait cycles that delay the progress of the pipeline.

Advantages of Pipelining:

  1. The cycle time of the processor is reduced, thus increasing instruction issue-rate in most cases.
  2. Some combinatorial circuits such as adders or multipliers can be made faster by adding more circuitry. If pipelining is used instead, it can save circuitry vs. a more complex combinatorial circuit.

Disadvantages of Pipelining:

  1. A non-pipelined processor executes only a single instruction at a time. This prevents branch delays (in effect, every branch is delayed) and problems with serial instructions being executed concurrently. Consequently the design is simpler and cheaper to manufacture.
  2. The instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent. This is due to the fact that extra flip flops must be added to the data path of a pipelined processor.
  3. A non-pipelined processor will have a stable instruction bandwidth. The performance of a pipelined processor is much harder to predict and may vary more widely between different programs.


Generic pipeline

Generic 4-stage pipeline; the colored boxes represent instructions independent of each other

To the right is a generic pipeline with four stages:

  1. Fetch
  2. Decode
  3. Execute
  4. Write-back

The top gray box is the list of instructions waiting to be executed; the bottom gray box is the list of instructions that have been completed; and the middle white box is the pipeline.

Execution is as follows:

Time Execution
0 Four instructions are awaiting to be executed
  • the green instruction is fetched from memory
  • the green instruction is decoded
  • the purple instruction is fetched from memory
  • the green instruction is executed (actual operation is performed)
  • the purple instruction is decoded
  • the blue instruction is fetched
  • the green instruction's results are written back to the register file or memory
  • the purple instruction is executed
  • the blue instruction is decoded
  • the red instruction is fetched
  • the green instruction is completed
  • the purple instruction is written back
  • the blue instruction is executed
  • the red instruction is decoded
  • The purple instruction is completed
  • the blue instruction is written back
  • the red instruction is executed
  • the blue instruction is completed
  • the red instruction is written back
  • the red instruction is completed
9 All instructions are executed


A bubble in cycle 3 delays execution
Main article: Bubble (computing)

When a "hiccup" in execution occurs, a "bubble" is created in the pipeline in which nothing useful happens. In cycle 2, the fetching of the purple instruction is delayed and the decoding stage in cycle 3 now contains a bubble. Everything "behind" the purple instruction is delayed as well but everything "ahead" of the purple instruction continues with execution.

Clearly, when compared to the execution above, the bubble yields a total execution time of 8 clock ticks instead of 7.

Bubbles are like stalls, in which nothing useful will happen for the fetch, decode, execute and writeback. It can be completed with a nop code.

Example 1

A typical instruction to add two numbers might be ADD A, B, C, which adds the values found in memory locations A and B, and then puts the result in memory location C. In a pipelined processor the pipeline controller would break this into a series of tasks similar to:

ADD R1, R2, R3
LOAD next instruction

The locations 'R1' and 'R2' are registers in the CPU. The values stored in memory locations labeled 'A' and 'B' are loaded (copied) into these registers, then added, and the result is stored in a memory location labeled 'C'.

In this example the pipeline is three stages long- load, execute, and store. Each of the steps are called pipeline stages.

On a non-pipelined processor, only one stage can be working at a time so the entire instruction has to complete before the next instruction can begin. On a pipelined processor, all of the stages can be working at once on different instructions. So when this instruction is at the execute stage, a second instruction will be at the decode stage and a 3rd instruction will be at the fetch stage.

Pipelining doesn't reduce the time it takes to complete an instruction rather it increases the number of instructions that can be processed at once and it reduces the delay between completed instructions- called 'throughput'. The more pipeline stages a processor has, the more instructions it can be working on at once and the less of a delay there is between completed instructions. Every microprocessor manufactured today uses at least 2 stages of pipeline.[citation needed] (The Atmel AVR and the PIC microcontroller each have a 2 stage pipeline). Intel Pentium 4 processors have 20 stage pipelines.

Example 2

To better visualize the concept, we can look at a theoretical 3-stage pipeline:

Stage Description
Load Read instruction from memory
Execute Execute instruction
Store Store result in memory and/or registers

and a pseudo-code assembly listing to be executed:

LOAD  #40, A      ; load 40 in A
MOVE A, B ; copy A in B
ADD #20, B ; add 20 to B
STORE B, 0x300 ; store B into memory cell 0x300

This is how it would be executed:

Clock 1
Load Execute Store

The LOAD instruction is fetched from memory.

Clock 2
Load Execute Store

The LOAD instruction is executed, while the MOVE instruction is fetched from memory.

Clock 3
Load Execute Store

The LOAD instruction is in the Store stage, where its result (the number 40) will be stored in the register A. In the meantime, the MOVE instruction is being executed. Since it must move the contents of A into B, it must wait for the ending of the LOAD instruction.

Clock 4
Load Execute Store

The STORE instruction is loaded, while the MOVE instruction is finishing off and the ADD is calculating.

And so on. Note that, sometimes, an instruction will depend on the result of another one (like our MOVE example). When more than one instruction references a particular location for an operand, either reading it (as an input) or writing it (as an output), executing those instructions in an order different from the original program order can lead to hazards (mentioned above). There are several established techniques for either preventing hazards from occurring, or working around them if they do.


Many designs include pipelines as long as 7, 10 and even 20 stages (like in the Intel Pentium 4) The later "Prescott" and "Cedar Mill" Pentium 4 cores (and their Pentium D derivatives) had a 31-stage pipeline, the longest in mainstream consumer computing. The Xelerator X10q has a pipeline more than a thousand stages long[1] . The downside of a long pipeline is when a program branches, the entire pipeline must be flushed, a problem that branch prediction helps to alleviate. Branch prediction itself can end up exacerbating the problem if branches are predicted poorly. In certain applications, such as supercomputing, programs are specially written to branch rarely and so very long pipelines are ideal to speed up the computations, as long pipelines are designed to reduce clocks per instruction (CPI). If branching happens constantly, re-ordering branches such that the more likely to be needed instructions are placed into the pipeline can significantly reduce the speed losses associated with having to flush failed branches. Programs such as gcov can be used to examine how often particular branches are actually executed using a technique known as coverage analysis, however such analysis is often a last resort for optimization.

The higher throughput of pipelines falls short when the executed code contains many branches: the processor cannot know where to read the next instruction, and must wait for the branch instruction to finish, leaving the pipeline behind it empty. After the branch is resolved, the next instruction has to travel all the way through the pipeline before its result becomes available and the processor appears to "work" again. In the extreme case, the performance of a pipelined processor could theoretically approach that of an un-pipelined processor, or even slightly worse if all but one pipeline stages are idle and a small overhead is present between stages.

Because of the instruction pipeline, code that the processor loads will not immediately execute. Due to this, updates in the code very near the current location of execution may not take effect because they are already loaded into the Prefetch Input Queue. Instruction caches make this phenomenon even worse. This is only relevant to self-modifying programs.

Minggu, 30 November 2008

Artikel Arkom 5


Memori akses acak (bahasa Inggris: Random access memory, RAM) adalah sebuah tipe penyimpanan komputer yang isinya dapat diakses dalam waktu yang tetap tidak memperdulikan letak data tersebut dalam memori. Ini berlawanan dengan alat memori urut, seperti tape magnetik, disk dan drum, di mana gerakan mekanikal dari media penyimpanan memaksa komputer untuk mengakses data secara berurutan.

Pertama kali dikenal pada tahun 60'an. Hanya saja saat itu memori semikonduktor belumlah populer karena harganya yang sangat mahal. Saat itu lebih lazim untuk menggunakan memori utama magnetic.

Perusahaan semikonduktor seperti Intel memulai debutnya dengan memproduksi RAM , lebih tepatnya jenis DRAM.

Biasanya RAM dapat ditulis dan dibaca, berlawanan dengan memori-baca-saja (read-only-memory, ROM), RAM biasanya digunakan untuk penyimpanan primer (memori utama) dalam komputer untuk digunakan dan mengubah informasi secara aktif, meskipun beberapa alat menggunakan beberapa jenis RAM untuk menyediakan penyimpanan sekunder jangka-panjang.

Tetapi ada juga yang berpendapat bahwa ROM merupakan jenis lain dari RAM, karena sifatnya yang sebenarnya juga Random Access seperti halnya SRAM ataupun DRAM. Hanya saja memang proses penulisan pada ROM membutuhkan proses khusus yang tidak semudah dan fleksibel seperti halnya pada SRAM atau DRAM. Selain itu beberapa bagian dari space addres RAM ( memori utama ) dari sebuah sistem yang dipetakan kedalam satu atau dua chip ROM.

Tipe umum RAM

Beberapa jenis RAM. Dari atas ke bawah: DIP, SIPP, SIMM 30 pin, SIMM 72 pin, DIMM, DDR DIMM.

Tipe tidak umum RAM

Produsen peringkat atas RAM

Artikel Arkom 4

Hirarki memori

Gambar Hierarki Memori Tradisional

Hierarki Memori atau Memory Hierarchy dalam arsitektur komputer adalah sebuah pedoman yang dilakukan oleh para perancang demi menyetarakan kapasitas, waktu akses, dan harga memori untuk tiap bitnya. Secara umum, hierarki memori terdapat dua macam yakni hierarki memori tradisional dan hierarki memori kontemporer.

Gambar Hierarki Memori Kontemporer

Hierarki memori memang disusun sedemikian rupa agar semakin ke bawah, memori dapat mengalami hal-hal berikut:

  • peningkatan waktu akses (access time) memori (semakin ke bawah semakin lambat, semakin ke atas semakin cepat)
  • peningkatan kapasitas (semakin ke bawah semakin besar, semakin ke atas semakin kecil)
  • peningkatan jarak dengan prosesor (semakin ke bawah semakin jauh, semakin ke atas semakin dekat)
  • penurunan harga memori tiap bitnya (semakin ke bawah semakin semakin murah, semakin ke atas semakin mahal)

Memori yang lebih kecil, lebih mahal dan lebih cepat diletakkan pada urutan teratas. Sehingga, jika diurutkan dari yang tercepat, maka urutannya adalah sebagai berikut:

  1. register mikroprosesor. Ukurannya yang paling kecil tapi memiliki waktu akses yang paling cepat, umumnya hanya 1 siklus CPU saja.
  2. Cache mikroprosesor, yang disusun berdasarkan kedekatannya dengan prosesor (level-1, level-2, level-3, dan seterusnya). Memori cache mikroprosesor dikelaskan ke dalam tingkatan-tingkatannya sendiri:
    1. level-1: memiliki ukuran paling kecil di antara semua cache, sekitar puluhan kilobyte saja. Kecepatannya paling cepat di antara semua cache.
    2. level-2: memiliki ukuran yang lebih besar dibandingkan dengan cache level-1, yakni sekitar 64 kilobyte, 256 kilobyte, 512 kilobyte, 1024 kilobyte, atau lebih besar. Meski demikian, kecepatannya lebih lambat dibandingkan dengan level-1, dengan nilai latency kira-kira 2 kali hingga 10 kali. Cache level-2 ini bersifat opsional. Beberapa prosesor murah dan prosesor sebelum Intel Pentium tidak memiliki cache level-2.
    3. level-3: memiliki ukuran yang lebih besar dibandingkan dengan cache level-2, yakni sekitar beberapa megabyte tapi agak lambat. Cache ini bersifat opsional. Umumnya digunakan pada prosesor-prosesor server dan workstation seperti Intel Xeon atau Intel Itanium. Beberapa prosesor desktop juga menawarkan cache level-3 (seperti halnya Intel Pentium Extreme Edition), meski ditebus dengan harga yang sangat tinggi.
  3. Memori utama: memiliki akses yang jauh lebih lambat dibandingkan dengan memori cache, dengan waktu akses hingga beberapa ratus siklus CPU, tapi ukurannya mencapai satuan gigabyte. Waktu akses pun kadang-kadang tidak seragam, khususnya dalam kasus mesin-mesin Non-uniform memory access (NUMA).
  4. Cache cakram magnetis, yang sebenarnya merupakan memori yang digunakan dalam memori utama untuk membantu kerja cakram magnetis.
  5. Cakram magnetis
  6. Tape magnetis
  7. Cakram Optik

Artikel Arkom 3

Penyimpanan data komputer

Penyimpanan data komputer, berasal dari bahasa Inggris "computer data storage" sering disebut sebagai memori komputer, merujuk kepada komponen komputer, perangkat komputer, dan media perekaman yang mempertahankan data digital yang digunakan untuk beberapa interval waktu. Penyimpanan data komputer menyediakan salah satu tiga fungsi inti dari komputer modern, yakni mempertahankan informasi. Ia merupakan salah satu komponen fundamental yang terdapat di dalam semua komputer modern, dan memiliki keterkaitan dengan mikroprosesor, dan menjadi model komputer yang digunakan semenjak 1940-an.

Dalam penggunaan kontemporer, memori komputer merujuk kepada bentuk media penyimpanan berbahan semikonduktor, yang dikenal dengan sebutan Random Access Memory (RAM), dan kadang-kadang dalam bentuk lainnya yang lebih cepat tapi hanya dapat menyimpan data secara sementara. Akan tetapi, istilah "computer storage" sekarang secara umum merujuk kepada media penyimpanan massal, yang bisa berupa cakram optis, beberapa bentuk media penyimpanan magnetis (seperti halnya hard disk) dan tipe-tipe media penyimpanan lainnya yang lebih lambat ketimbang RAM, tapi memiliki sifat lebih permanen, seperti flash memory.

Artikel Arkom 2

Bus sistem

System bus atau bus sistem, dalam arsitektur komputer merujuk pada bus yang digunakan oleh sistem komputer agar dapat berjalan. Sebuah bus adalah sebutan untuk jalur di mana data dapat mengalir dalam komputer. Jalur-jalur ini digunakan untuk komunikasi dan dapat dibuat antara dua elemen atau lebih.

Sebuah komputer memiliki beberapa bus, agar dapat berjalan. Banyaknya bus yang terdapat dalam sistem, tergantung dari arsitektur sistem komputer yang digunakan. Sebagai contoh, sebuah komputer PC dengan prosesor umumnya Intel Pentium 4 memiliki bus prosesor (Front-Side Bus), bus AGP, bus PCI, bus USB, bus ISA (yang digunakan oleh keyboard dan mouse), dan bus-bus lainnya.

Bus disusun secara hierarkis, karena setiap bus yang memiliki kecepatan rendah akan dihubungkan dengan bus yang memiliki kecepatan tinggi. Setiap perangkat di dalam sistem juga dihubungkan ke salah satu bus yang ada. Sebagai contoh, kartu grafis AGP akan dihubungkan ke bus AGP. Beberapa perangkat lainnya (utamanya chipset atau kontrolir) akan bertindak sebagai jembatan antara bus-bus yang berbeda. Sebagai contoh, sebuah kontrolir bus SCSI dapat mengubah sebuah bus menjadi bus SCSI, baik itu bus PCI atau bus PCI Express.

Beberapa bus utama dalam sistem komputer modern adalah sebagai berikut:

  • Bus prosesor. Bus ini merupakan bus tercepat dalam sistem dan menjadi bus inti dalam chipset dan motherboard. Bus ini utamanya digunakan oleh prosesor untuk meneruskan informasi dari prosesor ke cache atau memori utama ke chipset kontrolir memori (Northbridge, MCH, atau SPP). Bus ini juga terbagi atas beberapa macam, yakni Front-Side Bus, HyperTransport bus, dan beberapa bus lainnya. Sistem komputer selain Intel x86 mungkin memiliki bus-nya sendiri-sendiri. Bus ini berjalan pada kecepatan 100 MHz, 133 MHz, 200 MHz, 266 MHz, 400 MHz, 533 MHz, 800 MHz, 1000 MHz atau 1066 MHz. Umumnya, bus ini memiliki lebar lajur 64-bit, sehingga setiap detaknya ia mampu mentransfer 8 byte.
  • Bus AGP (Accelerated Graphic Port). Bus ini merupakan bus yang didesain secara spesifik untuk kartu grafis. Bus ini berjalan pada kecepatan 66 MHz (mode AGP 1x), 133 MHz (mode AGP 2x), atau 533 MHz (mode AGP 8x) pada lebar jalur 32-bit, sehingga bandwidth maksimum yang dapat diraih adalah 2133 MByte/s. Umumnya, bus ini terkoneksi ke chipset pengatur memori (Northbridge, Intel Memory Controller Hub, atau NVIDIA nForce SPP). Sebuah sistem hanya dapat menampung satu buah bus AGP. Mulai tahun 2005, saat PCI Express mulai marak digunakan, bus AGP ditinggalkan.
  • Bus PCI (Peripherals Component Interconnect). Bus ini berjalan pada kecepatan 33 MHz dengan lebar lajur 32-bit. Bus ini ditemukan pada hampir semua komputer PC yang beredar, dari mulai prosesor Intel 486 karena memang banyak kartu yang menggunakan bus ini, bahkan hingga saat ini. Bus ini dikontrol oleh chipset pengatur memori (northbridge, Intel MCH) atau Southbridge (Intel ICH, atau NVIDIA nForce MCP).
  • Bus PCI Express (Peripherals Component Interconnect Express)
  • Bus PCI-X (Peripherals Component Interconnect Express)
  • Bus ISA (Industry Standard Architecture)
  • Bus EISA (Extended Industry Standard Architecute)
  • Bus MCA (Micro Channel Architecture)
  • Bus SCSI (Small Computer System Interface]]
  • Bus USB (Universal Serial Bus)
  • Bus 1394

Artikel Arkom 1

Arsitektur komputer

Dari Wikipedia bahasa Indonesia, ensiklopedia bebas

Langsung ke: navigasi, cari
Abstraksi dari sebuah arsitektur komputer dan hubungannya dengan bagian perangkat keras, firmware, assembler, kernel, sistem operasi, dan perangkat lunak aplikasinya

Dalam bidang teknik komputer, arsitektur komputer adalah konsep perencanaan dan struktur pengoperasian dasar dari suatu sistem komputer. Arsitektur komputer ini merupakan rencana cetak-biru dan deskripsi fungsional dari kebutuhan bagian perangkat keras yang didesain (kecepatan proses dan sistem interkoneksinya). Dalam hal ini, implementasi perencanaan dari masing–masing bagian akan lebih difokuskan terutama, mengenai bagaimana CPU akan bekerja, dan mengenai cara pengaksesan data dan alamat dari dan ke memori cache, RAM, ROM, cakram keras, dll). Beberapa contoh dari arsitektur komputer ini adalah arsitektur von Neumann, CISC, RISC, blue Gene, dll.

Arsitektur komputer juga dapat didefinisikan dan dikategorikan sebagai ilmu dan sekaligus seni mengenai cara interkoneksi komponen-komponen perangkat keras untuk dapat menciptakan sebuah komputer yang memenuhi kebutuhan fungsional, kinerja, dan target biayanya.

Arsitektur komputer ini paling tidak mengandung 3 sub-kategori: